RTL Design

•RTL development & Integration

•Constraints Handling, Synthesis & STA.

•Functional Verification using SV/UVM.

•Static Verification.

Emulation and Modeling

•Building Emulation and Prototyping models

•Debugging designs on emulation platforms.

•Performance Modeling.

Physical Design

•Handling physical design flow from synthesis, to place and route to sign-off.

Design Verification using System Verilog/UVM